With the development of high-performance information devices and high-speed communications, a fine wiring and the like is formed in an electronic device to cope with a demand for a high-frequency signal or an increase in the number of signal wirings. It may be hard to apply a method for mounting a semiconductor device or an electronic component on a printed wiring board to a device requiring a high-frequency signal, since a variation and the like in electrical characteristics of wirings may affect a signal. Therefore, development of a wiring substrate capable of coping with a demand for a high-frequency signal has been progressing. As a technique of coping with a demand for a high-frequency signal or a high-density wiring, there is proposed a technique relating to a silicon interposer, for instance. A silicon interposer is configured such that semiconductor devices such as memory devices or arithmetic units are mounted on a silicon substrate, and the devices are connected to each other by wirings formed on the silicon substrate. In the silicon interposer, it is possible to reduce the wiring length or the wiring width by connecting the devices to each other by the wirings formed on the silicon substrate. This makes it possible to reduce a parasitic capacitance between the wirings or a variation in the wiring length, which are the problems in a high-frequency signal.
An influence of a parasitic capacitance may occur even if wirings are formed on a silicon substrate. The above configuration may be insufficient as a technique of coping with a demand for a further high-frequency signal or a further high-density wiring. In order to cope with a demand for a higher frequency-signal or a higher density wiring, it is necessary to provide a technique of further reducing the parasitic capacitance between the wirings for reducing a signal delay or signal attenuation resulting from the parasitic capacitance or the like. In view of the above, the technique of coping with a demand for a high-frequency signal or a high-density wiring such as reduction of a parasitic capacitance between wirings formed on a silicon substrate has been developing actively. As a technique relating to formation of wirings on a silicon substrate in order to cope with a demand for a high-frequency signal, there is disclosed a technique for instance, Patent Literature 1 (Japanese Laid-open Patent Publication No. 2010-68313).
Patent Literature 1 discloses a technique of reducing attenuation of a signal to be transmitted by a coplanar wiring formed on a silicon substrate. The coplanar wiring in Patent Literature 1 is formed on an insulating layer formed on a silicon substrate. In Patent Literature 1, an insulating layer between a signal wiring and a GND (Ground) wiring, and a region in the vicinity of a surface of a silicon substrate are removed. Patent Literature 1 discloses that removing the insulating layer between the signal wiring and the GND wiring makes it possible to prevent formation of a low-resistance layer, which may be a cause for leakage and the like of electricity in the vicinity of the interface between the insulating layer and the silicon substrate. In Patent Literature 1, forming the above structure makes it possible to reduce the thickness of the insulating layer to such a degree capable of insulating between the signal wiring and the GND wiring, and the silicon substrate. This is advantageous in easily manufacturing a coplanar wiring substrate. Thus, Patent Literature 1 discloses that it is possible to provide a coplanar wiring substrate at a low cost with ease.
Patent Literature 2 (International Laid-open Patent Publication No. 2007/083354) discloses a technique of reducing attenuation of a high-frequency signal in a wiring unit of a semiconductor device. The semiconductor device of Patent Literature 2 includes a structure with a SOI (Silicon On Insulator) layer, and includes a coplanar wiring unit formed on the upper portion of the SOI layer. In Patent Literature 2, a hollow portion is formed in a silicon substrate and the like at a position below a signal wiring. The hollow portion is not in a completely hollow state at a position right below the signal wiring, but a pillar remains in the hollow portion for preventing crush of the hollow portion. Patent Literature 2 discloses that forming a structure such that a pillar remains at a position right below the signal wiring makes it possible to form a large hollow portion, and this is advantageous in sufficiently reducing a dielectric loss. Patent Literature 2 discloses that, as a result, it is possible to reduce attenuation of a high-frequency signal, while securing reliability of the mechanical strength.
However, the technique of Patent Literature 1 has the following problem. In Patent Literature 1, an embedded portion of the insulating layer between the signal wiring and the GND wiring, and of the silicon substrate is formed by etching. As a pattern becomes finer by etching, the degree of difficulty of the etching process increases. Therefore, as the interval between signal wirings is narrowed, it may be difficult to form an embedded portion of the insulating layer and of the silicon substrate. Further, the degree of difficulty of the step of forming a structure having a corner portion such as a bent portion of a wiring by etching is high. The degree of difficulty of etching the structure further increases, as the pattern becomes finer. Thus, in the technique of Patent Literature 1, it may be difficult to form wirings requiring a fine and intricate circuit pattern.
Further, the technique of Patent Literature 2 has the following problem. In Patent Literature 2, a hollow portion is formed at a position right below the wiring. Therefore, it is necessary to form the hollow portion after an upper layer at a position above the hollow portion such as a SOI layer or a wiring layer is formed. In order to form the hollow portion at a position right below the SOI layer or the wiring layer, it is necessary to etch a lower layer via an opening portion, which is narrower than the hollow portion formed in the SOI layer or in the wiring layer. Therefore, it is difficult to control the process in the etching step, and a variation is likely to occur in the size of the hollow portion or of the pillar portion due to a difference in density of wirings. In particular, the influence is noticeable in forming a pattern having a narrow wiring interval. In the technique of Patent Literature 2, the process for forming a hollow portion may be complicated, and the number of steps may largely increase in order to precisely form the hollow portion on a fine pattern having a narrow wiring interval. Further, etching residues may remain in the hollow portion in a cleaning step and the like, which is performed after the hollow portion is formed. This may adversely affect the reliability. Therefore, the technique of Patent Literature 2 is also insufficient as a technique to be used in forming wirings requiring a fine and intricate circuit pattern.
An object of the invention is to provide a wiring substrate that enables to reduce attenuation of a signal without the need of complicated steps or the like, even when a fine and intricate wiring pattern is to be formed.